SELSE 2020 16th IEEE Workshop on Silicon Error in Logic

When:
February 19, 2020 – February 20, 2020 all-day
2020-02-19T00:00:00-08:00
2020-02-21T00:00:00-08:00
Where:
Stanford University
450 Serra Mall, Stanford, CA 94305
USA

SELSE – Silicon Errors in Logic – System Effects

The growing complexity and shrinking geometries of modern manufacturing technologies are making devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.

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