Reliability characterization of discrete devices and modeling circuit level aging in advanced CMOS technologies

January 10, 2019 @ 6:00 pm – 8:00 pm
Inc. 3165 Kifer Road Building-B Cafeteria Santa Clara

Tanya Nigam

Scaled transistor technologies encounter additional reliability challenges besides bias
temperature instability, time dependent dielectric breakdown and hot carrier
degradation. Time-zero variability and variability induced by device aging is a growing
concern which needs to be modeled using stochastic processes. The physical nature of
the stochastic process remains under debate and to support model development efforts
large statistical data sets are essential. In addition, self-heating during reliability testing
can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and
gate-all-around devices and needs proper attention. Apart from model development for
the individual reliability mechanisms, variability and self-heating, it is critical to provide a
platform integrating their impact for a circuit level assessment. In this presentation we
discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond
3s, address silicon validated modeling of degradation in RO/SRAM plus explore self-
heating effects in FinFET and SOI devices.

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